In general, manufacturing of a wafer level semiconductor package of a chip scale includes integrating circuits, such as transistors, on a wafer state semiconductor chip, forming a passivation film on a surface of the semiconductor chip to protect the semiconductor chip from external impacts, and forming a redistribution layer (RDL) that is a conductive metal interconnection line.
FIGS. 6A to 6G are cross-sectional views sequentially illustrating process operations of a method for manufacturing a conventional semiconductor package. A process of forming a conventional redistribution layer will now be described with reference to FIGS. 6A to 6G.
First, in an operation of providing a wafer, a designed circuit is integrated in a wafer-state semiconductor chip 10, and a bonding pad 12 is formed at a potential portion of an electrical input/output path of the circuit.
A die passivation 14 for protecting the integrated circuit is formed on the entire surface of the wafer-state semiconductor chip 10, and a first passivation film 16 is formed on the die passivation 14 (see FIG. 6A).
Here, a plurality of metal pads 12, sometimes called bonding pads 12, are formed on the semiconductor chip 10 in a predetermined array and exposed to the outside. Ends of a redistribution layer (RDL) 18 (FIG. 6C) are formed on the exposed bonding pads 12. The redistribution layer 18 includes metal interconnection lines for receiving a voltage for driving the circuit integrated in the semiconductor chip 10.
A seed layer 20 includes plating conductive lines for forming the redistribution layer 18. The seed layer 20 is formed throughout top surfaces of the first passivation film 16 and the bonding pad 12 by sputtering (see FIG. 6B).
Subsequently, photoresist 22 is coated throughout the surface of the wafer state semiconductor chip 10, and general exposure and development operations are performed on the photoresist 22, thereby exposing potential portions of the bonding pad 12 and the seed layer 20 on the semiconductor chip 10 (see FIG. 6B).
Subsequently, an electroplating process for forming the redistribution layer 18 is performed on the bonding pad 12 of the exposed semiconductor chip 10 and a potential region of a redistribution layer. If current is allowed to flow through the seed layer 20 in a state in which the seed layer 20 is put into a solution containing metal ions, the redistribution layer 18 is formed on a surface of the seed layer 20, that is, on a surface of the seed layer 20 formed on the bonding pad 12 and a surface of the potential region of a redistribution layer (see FIG. 6C).
Next, the photoresist 22 is stripped for removal (see FIG. 6D), and the remaining seed layer 20, except for the seed layer 20 existing under the redistribution layer 18, is removed through an etching process (see FIG. 6E), thereby completing formation of the redistribution layer 18 having predetermined area and length.
Meanwhile, a second passivation film 24 for preventing external impacts, moisture or other foreign materials from being applied to the redistribution layer 18 and preventing an electrical short from occurring to neighboring redistribution layers 18 is formed while encapsulating the redistribution layer 18 throughout the surfaces of the first passivation film 16 and the redistribution layer 18. An under bump metal (UBM) 30 that is a metallic electrode terminal is formed by plating a seed layer (not shown) at the other end of the redistribution layer 18 (see FIG. 6F).
Thereafter, the input/output terminal 32, such as a solder ball, is finally welded onto the under bump metal 30 (see FIG. 6G), thereby completing the wafer level package.
However, since a large number of process operations and an extended manufacturing time are required, the manufacturing method of the conventional wafer level package is problematic.
That is to say, after a photoresist for forming a redistribution layer is subjected to patterning and exposure and alignment, it is necessary to perform etching operations for removing the photoresist and the seed layer. That is to say, quite many process operations and extended time are required, resulting in an increase in the manufacturing cost.
In addition, as the wafer level package is manufactured to have a very small size, which is substantially the same as the size of each semiconductor chip, the input/output terminal 32, such as a solder ball, welded onto the under bump metal 30 needs to be very small. Accordingly, an adhered area of the input/output terminal 32 is very small, suggesting that the input/output terminal 32 has a weak adhesion strength at its adhering boundary. Thus, the input/output terminal 32 is prone to delamination even by trivial impacts.
Common reference numerals are used throughout the drawings and the detailed description to indicate the same elements.